December 04, 2007
Challenges in High Speed Reconfigurable Computing
As RPUs become more popular in high performance computing, programmers face challenges ranging from increasing demands for more bandwidth at lower latencies to dealing with non-parallelism inherent in certain algorithms. Several of these challenges are addressed by commercial RPUs, such as DRC's RPU110-L200.
By Michael Monkang Chu, published in FPGA Developer
PDF version
December 03, 2007
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
The University of Texas at Austin has published a paper examining FAST simulation technologies. The team used DRC hardware in their research. The following authors are credited: Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil,
William Reinhart, D. Eric Johnson, Jebediah Keefe and Hari Angepat.
PDF version via UT website
August, 2007
Filling the Need for Speed
In all aspects of business, from computing 3-D images of underground oil reserves from data collected by seismic testing, to searching huge databases, to rendering images in movies or medical scanners—doing more in less time has tremendous paybacks.
By Giang Le, published in Electronic Product Design
PDF version
July 25, 2007
FPGA-based hardware acceleration of C/C++ based applications
Steve Casselman explains how to accelerate C-based applications by running parallelized code on configurable processors.
By Steve Cassleman, published in PL DesignLine
PDF version
July 13, 2007
Standards-based Reconfigurable Computing
Users and developers have long recognized the enormous performance gains that reconfigurable hardware can provide for certain types of computationally intensive problems. However, a major barrier to widespread acceptance has been a lack of standards surrounding reconfigurable processors and the absence of a standardized system architecture. That's beginning to change.
By Michael D'Amour, published in HPCWire
PDF version
July 02, 2007
FPGA-based coprocessors simplify ASIC emulation
With compressed time lines and intense pressure to get it right the first time, ASIC emulation has become an increasingly critical part of the design process. Designers have historically had few good options for emulating ASICs, however. Now, many are turning to a new tool: FPGA-based coprocessors.
By Richard Povey, published in EETimes
PDF version
January 08, 2007
Reconfigurable Systems Craft a New Breed Of “Soft Appliances” that Deliver Topnotch Performance
As chip designs migrate down the process roadmap from 130 to 90 to 65nm and beyond, the cost of implementing a system-on-chip (SOC) solution doubles to triples at each smaller process node. The higher cost is forcing companies to consider a programmable off-the-shelf solution rather than an SOC design as a more cost-effective and more timely alternative.
By Michael D'Amour, published in SOCcentral
PDF version
