A: The high performance computing industry is growing faster than most other markets in IT. In fact, IDC estimates that the growth rate for HPC has been in excess of 3 percent since 2003. In addition, the 2007 revenue forecast for HPC is approximately $9 Billion. Growth is being driven by the fact that supercomputers are being more widely used in larger configurations than ever before.

A: If you take into account the number of applications where accelerators like DRC’s RPU could be deployed (approximately 15 to 20 percent of all microprocessors being sold into the HPC market), we estimate the market opportunity for 2007 to be in the neighborhood of $2 to $3 Billion.

A: DRC’s Reconfigurable Processor Unit effectively addresses HPC applications where performance and reliability are critical. DRC’s technology is also very suitable for large data centers where it can greatly increase performance of data mining applications such as searching, sorting, compressing, and encrypting and reduces the number of servers required for dramatic cost and power savings. We believe that the data center market will be our second largest target after high performance computing.

A: The DRC RPU is a system solution for solving compute-intensive problems and for accelerating high-performance applications. The RPU consists of DRC logic along with programmable hardware that plugs directly into an open processor socket in a multi-way AMD Opteron™ system. By accelerating high performance computing, our solution will help AMD gain increased market share.

A: There are two different issues here. Multicore is an architecture that addresses parallel processing, but it is still serial in terms of how it executes a given stream. With a FPGA or RPU, you can execute functions in a much more parallelized way than with a dual or quad core processor.
Nanotechnology is a fundamental semiconductor process technology used for creating a physical structure for storing or manipulating a single bit of information. It used to be that the driver for any new semiconductor process was the memory device because it has the simplest architectural structure and is therefore the easiest thing to debug. Most of the structures inside a FPGA are memory structures. So FPGAs are now a process driver. New technologies such as nanotechnology will actually drive FPGA growth even faster.

A: It’s a matter of an adopter demonstrating what can be accomplished in a given application area or vertical market. Once the advantages are shown in a real production environment, the rest of that industry has an easier time moving forward. The price-performance benefit is there, as are the "green-technology" or power savings benefits. The reduction in the number of nodes by five times or more has a dramatic impact on system management and footprint—another key advantage. Mass-market adoption, however, is reasonably assured given the support by most of the big players, namely Cray Inc., IBM, HP, Intel, and AMD, of hybrid compute platforms incorporating coprocessors or accelerators.

A: Each of these new technologies has much the same issue relative to software tools and development flow. If fact, so do multi-core CPUs. All these technologies require programs to be multi-threaded, meaning parallelized for performance. Once the application architects figure out what is necessary to parallelize at least portions of their code, a fine-grained implementation for an FPGA is not much different from a coarse-grained one for CPUs.
The FPGA turns out to be the most flexible architecture that can address the largest cross-section of compute intensive applications. It has logic that can stream or be conditional. The RPU has more memory bandwidth than any of the other technologies. There are multiple vendors supplying and developing tools and libraries.
GPUs will do well in highly streaming threads where no conditional processing is required—a small but meaningful subset of the co-processor market. Programming GPUs can be even more difficult than FPGAs or Cells, but an extensive library for the streaming applications has helped.
ClearSpeed-based technology has continually suffered from limited memory bandwidth and the ability to move data through the logic at high speed.
Cells are somewhere in between, but proprietary in nature because both hardware and compilers or tools are available only from that vendor.

A: We have demos and proof-of-concepts that we have shown publicly. Examples include everything from a programmed trading example in the financial market where we can give the trader a 30x to 50x advantage in reduced latency—which a publication states is worth a minimum of $100 million per year—to a seismic imaging application where the user gets the same performance as software running on a large cluster with a quarter the number of nodes and a fifth the amount of power consumed, at half the price.